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Micrel, Inc.
N, M, and A are numbers of length 12, 12 and 6 bits,
respectively The synthesizer’s output frequency can be
calculated from the following equation:
MICRF507
The input capacitance at the varactor pin must be taken
into consideration when designing the PLL loop filter. This
is most critical when designing a loop filter with high
f VCO f RF × 2
( 16 × N + A ) × 2 ( 16 × N + A )
f PD =
f XCO
M
=
=
bandwidth, which gives relatively small component values.
The input capacitance is approximately 6pF.
1 ≤ A ≤ 16
M≠0
540
RF Frequency vs Varactor Input Voltage
f RF = f XCO
where
16 × N + A
2M
530
520
510
500
490
480
11
10
01
f PD : Phase detector comparison frequency
f XCO : Crystal oscillator frequency
470
460
450
f VCO : Voltage controlled oscillator frequency
0
0.4
0.8
1.2
VARIN Voltage (V)
1.6
2
2.4
f RF : RF carrier frequency
Figure 13. RF Frequency vs. Varactor Voltage
The MICRF507 has two sets of register fields controlling
the synthesizer’s frequency multiplication ratio; A0/N0/M0
and A1/N1/M1. During transmission using divider
modulation (see “Divider Modulation” section), bit values of
‘0’ and ‘1’ respectively select the 0 and 1 register field set.
During reception and during transmission using VCO
modulation, only the 0 set is used.
VCO
The VCO has no external components.
The three-bit field VCO_IB controls VCO bias current to
optimize phase noise. The two bit field VCO_freq controls
a capacitor bank which determines the VCO frequency
range. These five bits are set according to the RF
frequency as follows:
and VCO_ Freq bits (V DD = 2.5V)
Charge Pump
The charge pump current can be set to either 125μA or
500μA by CP_HI (‘1’ → 500μA). This will affect the loop
gain and, consequently, filter component values. For
applications using high phase detector frequency and high
PLL bandwidth, use 500μA charge pump current.
PLL Filter
The design of the PLL filter strongly affects the
performance of the frequency synthesizer. Key parameters
in PLL filter design are loop bandwidth, the modulation
method (VCO modulation or divider modulation) and the
bit rate. Filter design also affect the switching time
(important when frequency hopping) and phase noise.
RF
Freq
VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0
Divider modulation requires the PLL to lock on a new
carrier frequency for every new data bit. As a rule of
470-
482MHz
482-
497MHz
497-
510MHz
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
thumb, the PLL loop bandwidth should be at least twice as
high as the bit rate. In such cases it is recommended to
use a third order filter to suppress the phase detector
frequency.
For VCO modulation, the PLL loop bandwidth should be
less than 1/10 of the bit rate. If the loop bandwidth is high
relative to the bit rate, the PLL will keep the VCO at a fixed
Table 11. VCO Bit Setting
The tuning range, the RF frequency versus VCO tune
voltage (varactor input, pin 29), depends on the VCO
frequency setting as shown in as shown in Figure 13.
When the tuning voltage is in the range from 0.9V to 1.4V,
the VCO gain (as seen by the PLL) is at its maximum,
approximately 64 to 70MHz/V. Note that the RF frequency
is half of the PLL frequency. It is recommended that the
VCO tune voltage stays in this range.
frequency, preventing it from being modulated.
The recommended third-order loop filter (made with
external components) is shown in Figure 14. When R2=0
and C3 is omitted, this reduces to a second-order loop
filter.
October 2, 2013
22
Revision 2.2
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